Neuromorphic computation with spiking memristors: habituation, experimental instantiation of logic gates and a novel sequence-sensitive perceptron model

Memristors have been compared to neurons and synapses, suggesting they would be good for neuromorphic computing. A change in voltage across a memristor causes a current spike which imparts a short-term memory to a memristor, allowing for through-time computation, which can do arithmeticaL operations and sequential Logic, or mode[ short-time habituation to a stimulus. Using simpLe physical rules, simpLe Logic gates such as XOR, and novel, more complex, gates such as the arithmetic fuLL adder (AFA) can be instantiated in soL-geL TiO2 plastic memristors. The adder makes use of the memristor's short-term memory to add together three binary values and outputs the sum, the carry digit and even the order they were input in, allowing for logically (but not physically reversible) computation. Only a singLe memristor is required to instantiate each gate, as additional input/output ports can be replaced with extra time-steps allowing a singLe memristor to do a hitherto unexpectedly Large amount of computation, which may mitigate the memristor's sLow operation speed and may relate to how neurons do a similarly Large computation with sLow operation speeds. These Logic gates can be understood by modelling the memristors as a novel type of perceptron: one which is sensitive to input order. The memristor's short-term memory can change the input weights applied to Later inputs, and thus the memristor gates cannot be accurately described by a singLe perceptron, requiring either a network of time-invariant perceptrons, or a sequence-sensitive seLf-reprogrammabLe perceptron. Thus, the AFA is best described as a sequence sensitive perceptron that sorts binary inputs into classes corresponding to the arithmeticaL sum of the inputs. Co-development of memristor hardware alongside software (sequence-sensitive perceptron) models in trained neuraL networks would allow the porting of modern deep-neuraL networks architecture to [ow-power hardware neuraL net chips.