CMOS implementation of a novel analog multiplier/divider to realize centroid strategy in defuzzifier block

This paper, presents a CMOS design of a novel current-mode analog multiplier/divider which can be used in defuzzifier block for fuzzy logic controllers (FLC) and neuro-fuzzy systems to realize the centroid strategy. This analog multiplier/divider circuit operates based on the square-law characteristic of a MOS transistor operated in the saturation region. The proposed circuits are designed in 0.18 mu m CMOS technology with a power supply of 2 Volt. The maximum delay for the proposed circuit is 50.7 ns that restricts the inference speed of the total fuzzy logic controller to 20 MFLIPS in its turn. The maximum power consumption of this circuit is about 626 mu W and can be implemented in 84 mu mx36 mu m. The functionality of the proposed multiplier/divider in the defuzzifier block of a typical (3x3) FLC was evaluated and results indicate that the percentage of root mean squarer error (RMSE) of the output surface is 1.08% of the full scale output. To obtain the ideal output surface MATLAB software has been utilized.