期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 37, 期 3, 页码 404-412出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/4.987093
关键词
CMOS digital integrated circuits; decoding; error correction coding; parallel architectures
A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of I Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply.
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