Manufacturing costs for microsystems/MEMS using high aspect ratio microfabrication techniques

The emphasis on high aspect ratio micromachining techniques for microsystems/MEMS has been mainly to achieve novel devices with, for example, high sensing or actuation performance. Often these utilize deep structures (100-1,000 mu m) with vertical wall layers but with relatively modest spatial resolution (1-10 mu m). As these techniques move from research to industrial manufacture, the capital cost of the equipment and the cost of device manufacture become important, particularly where more than one micromachining technique can meet the performance requirements. This paper investigates the layer-processing costs associated with the principal high aspect ratio micromachining techniques used in microsystems/MEMS fabrication, particularly silicon surface micromachining, wet bulk etching, wafer bonding, Deep Reactive Ion Etching, excimer laser micromachining, UV LIGA and X-ray LIGA. A cost model (MEMSCOST) has been developed which takes the financial, operational and machine-dependent parameters of the different manufacturing techniques as inputs and calculates the layer-processing costs at the wafer and chip level as a function of demand volume. The associated operational and investment costs are also calculated. Cost reductions through increases in the wafer size and decreases in chip area are investigated, and the importance of packaging costs demonstrated.