Selective epitaxial Si/SiGe growth for V-T shift adjustment in high k pMOS devices

Downscaling of classical metal oxide semiconductor (MOS) devices resulted in a need to replace the gate oxide by high k dielectrics to keep the gate leakage under control. However, new device issues such as an uncontrollable shift in the threshold voltage in p-type MOS devices and a reduction in channel mobility were encountered. These issues can be overcome by the implementation of buried strained SiGe channels, grown by selective epitaxial growth, as demonstrated in this paper. The optimized high k gate fabrication scheme starts with the growth of a very thin oxide layer. Therefore, a Si cap layer is required because oxidation of SiGe leads to defects at the gate/channel interface. The Si growth rate is influenced by the underlying SiGe layer, during the deposition of the first atomic layers. Nevertheless, accurate thickness control of the Si cap is possible. The minimal required Si cap thickness and its dependence on Ge content in the underlying SiGe channel, for making high-quality dielectrics and maintaining low capacitive equivalent thickness, is extracted from charge pumping measurements, CV measurements and energy dispersive x-ray spectroscopy measurements. Device results demonstrate the successful implementation of buried SiGe channels in pMOS devices with high k gate dielectrics.