期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 35, 期 11, 页码 1655-1667出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/4.881212
关键词
balanced/unbalanced sensing scheme; burst read; error correction code; multilevel cell; NOR flash memory; simultaneous programming
This paper presents a 3-V-only 64-Mb 4-level-cell (2-b/cell) NOR-type channel-hot electron (CHE) programmed flash memory fabricated in 0.18-mum shallow-trench isolation CMOS technology. The device (die size 40 mm(2)) is organized in 64 1-Mb sectors. Hierarchical column and row decoding ensures complete isolation between different sectors during any operation, thereby increasing device reliability while still providing layout area optimization. Staircase gate-voltage programming is used to achieve narrow threshold-voltage distributions. The same program throughput as for bilevel CHE-programmed memories is obtained, thanks to parallel programming. A mixed balanced/unbalanced sensing approach allows efficient use of the available threshold window Asynchronous (130-ns access time) and burst-mode (up to 50-MHz data rate) reading is possible. Both column and row redundancy is provided to ensure extended failure coverage. Error correction code techniques, correcting 1 failed over 32 data cells, are also integrated.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据