期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 48, 期 5, 页码 921-927出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/16.918240
关键词
analog circuits; CMOS transistors; low noise; 1/f noise
Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two low noise CMOS processes of 2 mum and 0.5 mum technologies are compared and it is found that the more advanced process, with 0.5 mum technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits.
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