期刊
SOLID-STATE ELECTRONICS
卷 45, 期 9, 页码 1659-1664出版社
PERGAMON-ELSEVIER SCIENCE LTD
DOI: 10.1016/S0038-1101(01)00052-1
关键词
SiC; edge termination; junction termination extension; breakdown; simulation
The design of SiC planar and non-planar junction termination extension (JTE) structures are investigated through calibrated quasi-3D numerical simulation. JTE techniques are optimized with respect to breakdown voltage, area consumption, surface fields, and interface charge. Simulated JTE charge profiles predict near-ideal breakdown values with surface fields less than 60% of their bulk values, and show that the critical implant activation percentage can vary as much as 40%, with only 10% reduction in breakdown voltage for lightly doped blocking layers. These results are extended to unique multiple-zone JTE and mesa-JTE structures applicable to a wide range of planar and non-planar SiC power devices. (C) 2001 Published by Elsevier Science Ltd.
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