期刊
INTEGRATION-THE VLSI JOURNAL
卷 31, 期 1, 页码 79-100出版社
ELSEVIER SCIENCE BV
DOI: 10.1016/S0167-9260(01)00023-2
关键词
image coding; motion estimation; very large scale integration (VLSI); high-speed integrated circuits; low-power circuits
This paper presents a VLSI macro-cell for the implementation of full-search (FS) motion estimation that is a key issue of various video processing and compression standards such as MPEG and H.263. Beyond the usual algorithm, advanced-prediction and static-priority options are supported to improve the SNR/bit-rate efficiency. The architecture is fully parametric in terms of block size and maximum search area size and the latter is also dynamically programmable. Based on a hardware multiplexing strategy and a saturation mechanism, the architecture features high throughput/area efficiency and reduced hardware complexity with respect to conventional FS systolic arrays. Two ASICs were implemented on a 0.25 mum CMOS technology. The high-speed one features a 5.4 mm(2) core size and processes up to 4CIF format at 105 MHz. The smaller one features a 2 mm(2) core size and processes QCIF and CIF formats at 18 and 72 MHz, respectively. Exploiting the search area size programmability, these two formats can be processed with an average power consumption of 16 and 65 mW, respectively, which is of paramount interest for wireless applications. (C) 2001 Elsevier Science B.V. All rights reserved.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据