期刊
JOURNAL OF MICROMECHANICS AND MICROENGINEERING
卷 11, 期 6, 页码 630-634出版社
IOP PUBLISHING LTD
DOI: 10.1088/0960-1317/11/6/303
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The fabrication and reliability of a solder wafer-to-wafer bonding process is discussed. Using a solder reflow process allows vacuum packaging to be accomplished with unplanarized complementary metal-oxide semiconductor (CMOS) surface topography. This capability enables standard CMOS processes, and integrated microelectromechanical systems devices to be packaged at the chip-level. Alloy variations give this process the ability to bond at lower temperatures than most alternatives. Factors affecting hermeticity, shorts, Q values, shifting cavity pressure, wafer saw cleanliness and corrosion resistance will be covered.
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