Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip

Reasons for current trade-off of test data volume for scan power dissipation in system-on-chip (SOC) testing is investigated. The conflict between the existing compression method and scan power minimisation technique is understood and it is proved that by using a new compression method this trade-off is unnecessary. When the new compression method is combined with scan latch reordering savings of up to 97% in peak power and 99% in average power, as well as compression ratios of up to 95% are possible.