期刊
IEEE ELECTRON DEVICE LETTERS
卷 23, 期 6, 页码 345-347出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2002.1004230
关键词
double-gate MOSFETs; fully depleted; silicon-on-insulator (SOI) MOSFETs; scaled CMOS; DRAM
A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off-state leakage and disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dV(T))/(dV(BS))) transforms small gains of body potential into increased drain current. MEDICI simulations for 85degreesC show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies.
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