Effects of film morphology and gate dielectric surface preparation on the electrical characteristics of organic-vapor-phase-deposited pentacene thin-film transistors

Organic vapor phase deposition was used to grow polycrystalline pentacene channel thin-film transistors. Substrate temperature, chamber pressure during film deposition, and growth rate were used to vary the crystalline grain size of pentacene films on O-2-plasma treated SiO2 from 0.2 to 5 mum, leading to room-temperature saturation regime field-effect hole mobilities (mu(eff)) from 0.05+/-0.02 to 0.5+/-0.1 cm(2)/V s, respectively. Surface treatment of SiO2 with octadecyltrichlorosilane (OTS) prior to pentacene deposition resulted in mu(eff)less than or equal to1.6 cm(2)/V s, and drain current on/off ratios of less than or equal to10(8) at room temperature, while dramatically reducing the average grain size. X-ray diffraction studies indicate that the OTS treatment decreases the order of the molecular stacks. This suggests an increased density of flat-lying molecules, accompanying the improvement of the hole mobility at the pentacene/OTS interface. (C) 2002 American Institute of Physics.