Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

A spacer lithography technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are finished not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern silicon-fin structures for double-gate MOSFETs and CMOS FinFET results are reported. (C) 2002 Elsevier Science Ltd. All rights reserved.