期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 38, 期 5, 页码 782-792出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2003.810052
关键词
constant envelope modulation; fractional-N; frequency synthesis; GSM; noise filtering; sigma-lelta; transmitter; voltage-controlled oscillator (VCO)
A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a, receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-mum CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13=MHz offset is -77 dBc.
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