4.5 Article Proceedings Paper

3-D electronics interconnect for high-performance imaging detectors

期刊

IEEE TRANSACTIONS ON NUCLEAR SCIENCE
卷 51, 期 4, 页码 1829-1834

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2004.832712

关键词

adaptive lithography; die stacking; fast imagers; HDI; polymer bump bonding; 3-D interconnect

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We describe work that extends three-dimensional (3-D) patterned overlay high-density interconnect (HDI) to high-performance imaging applications. The work was motivated by the rigorous requirements of the multiple-pulse imager for dynamic proton radiography. The optical imager has to provide large (>90%) optical fill factor, high quantum efficiency, 200-ns inter-frame time interval, and storage for >32 frames. In order to accommodate the massively parallel electronics including the signal storage for a large number of frames, it is necessary to provide novel 3-D interconnect and packaging architectures. Recently, a 3-D interconnect technology was successfully demonstrated to assemble a stack of 50 signal-processing chips into a cube. Each chip contained test connections (interconnect continuity only) simulating 166 channels of pixel read-out electronics. Test cube assemblies, based on these mock-up integrated circuits, have been fabricated to explore the feasibility of constructing functional cube arrays. A novel 3-D integrated sensor-electronics (mirror-cube) imager architecture is proposed. We also briefly review progress in the custom fast image-processing electronics.

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