Proposal for all-graphene monolithic logic circuits

Since the very inception of integrated circuits, dissimilar materials have been used for fabricating devices and interconnects. Typically, semiconductors are used for devices and metals are used for interconnecting them. This, however, leads to a contact resistance between them that degrades device and circuit performance, especially for nanoscale technologies. This letter introduces and explores an all-graphene device-interconnect co-design scheme, where a single 2-dimensional sheet of monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the use of external contacts is alleviated, resulting in substantial reduction in contact parasitics. Calculations based on tight-binding theory and Non-Equilibrium Green's Function (NEGF) formalism solved self-consistently with the Poisson's equation are used to analyze the intricate properties of the proposed structure. This constitutes the first NEGF simulation based demonstration that devices and interconnects can be built using the same starting material - graphene. Moreover, it is also shown that all-graphene circuits can surpass the static performances of the 22 nm complementary metal-oxide-semiconductor devices, including minimum operable supply voltage, static noise margin, and power consumption. (C) 2013 AIP Publishing LLC.