Effects of sidewall etching on electrical properties of SiOx resistive random access memory

The electroforming voltages (V-ef) of silicon oxide resistive random access memory devices with oxide sidewall etched to different degrees are compared. The results show that the Vef is significantly reduced when more sidewall area is formed, and Vef of around 17 V is achieved in devices with maximum sidewall area. Plausible electroforming and state switching mechanisms are discussed using a filament-gap model. Endurance measurements up to 10 7 pulse cycles are compared for different device types. An external series resistance may be helpful for decreasing voltage stress during pulsed cycling to help enable device survival beyond 10 7 pulse cycles. (C) 2013 AIP Publishing LLC.