期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 51, 期 11, 页码 1772-1782出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2004.837369
关键词
analog hardware description language (AHDL); CMOS-nano codesign; computer-aided design (CAD); Coulomb blockade; hybrid circuits; master equation circuit simulation; Monte Carlo simulation; semiconductor device modeling; single electron transistor (SET)
A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the orthodox theory of single electron tunneling, and valid for single:or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (\V-DS\ less than or equal to 3e/C-Sigma) and temperatures [T less than or equal to e(2)/(10k(B)C(Sigma))] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据