期刊
APPLIED PHYSICS LETTERS
卷 92, 期 20, 页码 -出版社
AMER INST PHYSICS
DOI: 10.1063/1.2928234
关键词
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资金
- Direct For Mathematical & Physical Scien
- Division Of Materials Research [0748910] Funding Source: National Science Foundation
We developed a multilevel lithography process to fabricate graphene p-n-p junctions with contactless, suspended top gates. This fabrication procedure minimizes damage or doping to the single atomic layer, which is only exposed to conventional resists and developers. The process does not require special equipment for depositing gate dielectrics or releasing sacrificial layers, and is compatible with annealing procedures that improve device mobility. Using this technique, we fabricate graphene devices with suspended local top gates, where the creation of high quality graphene p-n-p junctions is confirmed by transport data at zero and high magnetic fields. (C) 2008 American Institute of Physics.
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