(110)-surface strained-SOI CMOS devices

We have newly developed (110)-surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on (110)-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on (110)-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of (110)-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of (110)-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of (110)-surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the (110)-surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a (110)-surface Si. As a result, the (110)-surface strained-SOI technology with optimization of the current flow directions of nand p-MOS is promising for realizing higher speed scaled CMOS.