4.4 Article Proceedings Paper

Breakdowns in high-k gate stacks of nano-scale CMOS devices

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MICROELECTRONIC ENGINEERING
卷 80, 期 -, 页码 353-361

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ELSEVIER
DOI: 10.1016/j.mee.2005.04.091

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high-k; CMOS; breakdown; gate dielectrics; MOSFET

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New failure mechanisms associated with breakdown in high-k gate stack consisting of HfO2/SiOx bilayered structure are presented. In addition to dielectric-breakdown-induced epitaxy (DBIE) commonly found in breakdowns in poly-Si/SiOxNy and poly-Si/S i(3)N(4) MOSFETs, grain-boundary and field-assisted breakdowns near the poly-Si edge are found. A model based on breakdown induced thermo-chemical reactions has been developed to describe the physical microstructural damages triggered by breakdown in the high-k gate stack and the associated post-breakdown electrical performance. Some abnormal post-breakdown electrical behaviors such as recouping of the transistor's saturated drain current, percolation resistance and transconductance are found to be common for high-k MOSFETs. Grain-boundary enhanced breakdown in annealed HfO2 films is of critical importance in degrading the reliability of high-k gate stacks.

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