Single machine scheduling with multiple objectives in semiconductor manufacturing

To deal with today's stiff competition in the logistics of semiconductor manufacturing, the development of an efficient scheduling approach for the complex semiconductor back-end testing operations is very essential, where more than one objective, such as cycle time, machine utilization and due date accuracy are kept in the focus to various degrees simultaneously. In this paper, the problem of scheduling N independent jobs on a single testing machine with due dates and sequence-dependent setup times is addressed, where the multiple objectives are to minimize average cycle time and average tardiness and to maximize machine utilization. A near optimal solution, which is not inferior to any other feasible solution in terms of all objectives, is generated combining the analytically optimal and conjunctive simulated scheduling approach. First, the machine-scheduling problem is modeled using the discrete event simulation approach and the problem is divided into simulation clock-based lot selection sub-problems. Then, at each decision instance in simulated time, a Pareto optimal lot is selected using the compromise programming technique for multi-objective optimization. With the help of a broad experimental design, this developed solution is then compared with common heuristic-dispatching rules used in industry such as the shortest processing time (SPT) and earliest due date (EDD). The developed scheduling method shows better results for all the objectives over a wide range of problems. It shows approximately 16.7% reduction in average cycle time, 25.6% reduction in average tardiness, and 21.6% improvement in machine utilization over the common dispatching rules, SPT and EDD.