期刊
IEEE TRANSACTIONS ON NANOTECHNOLOGY
卷 4, 期 6, 页码 669-680出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNANO.2005.858609
关键词
full adders (FAs); sensitivity to variations; single-electron technology (SET); threshold logic
This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据