Electrical barriers in the ZnO varistor grain boundaries

In this paper a detailed nature of the electrical potential barriers in ZnO based varistors are presented. The excellent nonlinear current-voltage (I-V) characteristic of these varistors is attributed to the potential barriers formed between the successive ZnO grains during the processing cycle. These grain boundaries in the microstructure results in a few device-related parameters such as built-in-potential, barrier height, barrier width, grain carrier density, Fermi level position in the grains, etc. Thermal activation energy is determined from the status of the leakage current of this device. Substantial studies conducted to comprehend possible conduction processes in the grain boundary regions under applied bias (electric field). It is understood that electron transport dominate the grain boundary regions based on electrical potential barrier consideration across the grain boundaries. The free electrons overcome potential barrier at elevated temperatures as well as under bias. These carriers fill trap sites (charged defect states) both in the bulk ZnO and in the grain surfaces (surface states). The formation of space charge region within the successive ZnO grains across the grain boundaries is a result of the equilibrium state of the device. Based on the findings an expression of the Schottky potential barrier width is proposed satisfying relevant expression of the current caused by the application of the electric field. It is observed that the potential barrier width is sharply reduced in the temperature range 320 K <= T <= 350 K. This reduction in the potential barrier width is likely to be associated with the relaxation process of the trap filled (trapped) carriers, usually monitored by the dielectric response (in the form of differential capacitance) of the device. Thus, the results provide an improved understanding of the nonlinear conduction behavior in ZnO varistors. (c) 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.