High-performance fully depleted silicon-nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with <= 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g-, near ideal subthreshold slope (similar to 63 mWdec), low drain-induced barrier lowering (similar to 10 V/V), and with I-ON/I-OFF ratio of similar to 10(6). High drive currents of similar to 1.5 and similar to 1.0 mA/mu m were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.