Uniaxial-process-induced strained-Si: Extending the CMOS roadmap

This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-mn logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k center dot p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on (001) and (110) wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on (001) or (110) wafers and (110) channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be similar to 4 times higher for uniaxial stress on (100) wafer and similar to 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a (110) wafer.