High-speed JPEG coder implementation for a smart camera

The compression standard of the Joint Photographic Experts Group (JPEG) for still images is used in many imaging applications. Although machine vision algorithms are based on raw images, massive data reduction of images in many applications is required additionally, e.g. to archive images in the context of automated visual inspection or to store highspeed image sequences when memory space is limited. Especially in embedded systems the software implementation of compression algorithms is too slow to meet real-time requirements. In this paper we present a fast implementation of a JPEG coder in a field programmable gate array (FPGA). This JPEG coder uses the architecture-specific function blocks of a low-cost FPGA (dedicated multipliers, block RAM). Nevertheless, there is hardly any limitation to the generality of the approach, as these building blocks are manufacturer-independent elements of up-to-date FPGA architectures.