Design optimization of metal nanocrystal memory - Part II: Gate-stack engineering

Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-kappa control and tunneling oxides. The high-kappa control oxide enables the effectiveoxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-kappa tunneling oxide, on the other hand, improves the retention characteristics utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally with the optimization strategies introduced in both Parts I an II, a metal NC memory design with 1.0-V memory window, 13-mu s programming, 2.5-mu s erasing, and over 10-year retention time has been demonstrated at +/- 4-V operation, which highlights the potent tial of NC memories as the next-generation nonvolatile memory.