期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 41, 期 12, 页码 2767-2775出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2006.884802
关键词
CMOS integrated circuits; IEEE 802.15.4; low-IF receiver; low-noise amplifier; power amplifier; radio transceivers; single-chip radio; spread-spectrum communication; switching mixers; wireless communication; WPAN
A single-chip 2.4-GHz CMOS radio transceiver with integrated, baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1 % packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4 in in receive mode and features bidirectional RF pins. The 5.77 mm(2) chip is implemented in a standard 0.18-mu m CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port.
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