期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 54, 期 2, 页码 359-362出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2006.888674
关键词
doubly stacked; ion beam sputtering (IBS); nonvolatile memory (NVM); Si nanocrystals (NCs); ultrahigh vacuum (UHV)
资金
- Ministry of Education, Science & Technology (MoST), Republic of Korea [07-2501-906] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
- National Research Foundation of Korea [핵06A2802, 과06A1604] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)
Structures of SiO2/SiOx/SiO2 and SiO2/SiOx/SiO2/SiOx/SiO2 have been prepared on Si wafers by ion beam sputtering deposition in ultrahigh vacuum (UHV) and subsequently annealed to form single-laver and doubly stacked Si nanocrystals (NCs). Using these two structures, nonvolatile Si-NC floating-gate nMOSFETs were fabricated at x = 1.6 following 1.5-mu m CMOS standard procedures. The Fowler-Nordheim tunneling of the electrons through the tunnel oxide, their storage into NCs, retention, and endurance are all investigated by varying the device structure and the thicknesses of the NC and oxide layers. It is shown that charge-retention time is longer, and program/erase (P/E) speeds are faster in doubly stacked devices than in single-layer devices, which seem to result from the optimization of device structure, the exclusion of unwanted defects due to the nature of UHV, and the suppression of charge leakage by the multiple barriers/NC layers in the doubly stacked devices. It is also found that the threshold voltages in the endurance characteristics anomalously increase with the P/E cycles, more strongly in the doubly stacked NC memories.
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