期刊
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
卷 15, 期 3, 页码 346-357出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2007.893624
关键词
address event representation (AER); CMOS image sensors; on-chip histogram equalization; time-to-first spike (TFS) vision sensor
This paper presents a time-to-first spike (TFS) and address event representation (AER)-based CMOS vision sensor performing image capture and on-chip histogram equalization (HE). The pixel values are read-out using an asynchronous hand-shaking type of read-out, while the HE processing is carried out using simple and yet robust digital timer occupying a very small silicon area (0.1 x 0.6 mm(2)). Low-power operation (10 nA per pixel) is achieved since the pixels are only allowed to switch once per frame. Once the pixel is acknowledged, it is granted access to the bus and then forced into a stand-by mode until the next frame cycle starts again. Timing errors inherent in AER-type of imagers are reduced using a number of novel techniques such as fair and fast arbitration using toggled priority (TP), higher-radix, and pipelined arbitration. A verilog simulator was developed in order to simulate the effect of timing errors encountered in AER-based imagers. A prototype chip was implemented in ANUS 0.35 mu m process with a silicon area of 3.1 x 3.2 mm(2). Successful operation of the prototype is illustrated through experimental measurements.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据