Nanoscale electrical characterization of Si-nc based memory metal-oxide-semiconductor devices

In this work, standard and nanoscale experiments have been combined to investigate the electrical properties of metal-oxide-semiconductor (MOS) memory devices with silicon nanocrystals (Si-nc) embedded in the gate oxide. The nanometer scale analysis has been performed with a conductive atomic force microscope (C-AFM) which, thanks to its high lateral resolution, allows the study of areas of only few hundreds of nm(2). Therefore, with this technique, a very reduced number of Si-nc can be investigated. We have studied the conduction mechanisms, the retention time, and the amount of charge stored in the Si-nc of these structures. The results have demonstrated that Si-nc enhance the gate oxide electrical conduction due to trap assisted tunneling. On the other hand, Si-nc can act as trapping sites. The amount of charge stored in Si-nc has been estimated through the change induced in the barrier height measured from the current-voltage (I-V) curves (at the nanoscale, with C-AFM) and from the flat band voltage shift determined from the capacitance-voltage (C-V) characteristics measured on polygated structures. Both procedures have shown an occupation level of similar to 20% of the Si-nc. The retention times, estimated at the nanoscale and from standard electrical characterization, are consistent. Moreover, contrary to standard characterization techniques, C-AFM allows the mesurement of lateral leakage currents in memories based on high density trapping sites. All these results allow one to conclude that C-AFM is a very suitable tool in performing a detailed investigation of the performance of memory devices based on MOS structures with Si-nc at the nanoscale.