期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 54, 期 9, 页码 2377-2385出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2007.902047
关键词
cylindrical conducting channels; electrostatic capacitance; modeling; planar gate; 1-D field-effect transistors (1-D FETs)
This paper presents accurate analytical models to calculate the electrostatic gate capacitance of I-D field-effect transistors (FETs) -with multiple cylindrical conducting channels. Gate capacitance C-gg is decomposed into three major components: 1) capacitance C-gc between the gate and the parallel cylindrical conducting channels (the number of channels >= 1) in dual-layer dielectric materials; 2) outer fringe capacitance C-of between the gate and the source/drain cylinder conductors; and 3) coupling capacitance C-gtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.
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