On-chip interconnection architecture of the tile processor

Imesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2d mesh networks, each specialized for a different use. Taking advantage of the five networks, the cbased ilib interconnection library efficiently maps program communication across the on-chip interconnect. The tile processor's first implementation, the tile64, contains 64 cores and can execute 192 billion 32-bit operations per second at 1 GHz.