Analysis and modeling of an improved dual-array D/A network for SAR A/D converter

Based on the discussion of traditional dual-array charge scaling D/A conversion approach, an improved D/A network for successive approximation A/D converter (ADC) is proposed in this letter. With a unit capacitor instead of traditional non-integral scaling capacitor and by adding several additional logic control signals, this novel D/A network is easier to realize in process than traditional dual-array approach. Theoretical analysis and high-level Matlab modeling results prove that this improved D/A network is suitable for embedded SoC applications.