期刊
IET POWER ELECTRONICS
卷 8, 期 12, 页码 2435-2443出版社
INST ENGINEERING TECHNOLOGY-IET
DOI: 10.1049/iet-pel.2014.0878
关键词
reference circuits; phase locked loops; transient response; state-space methods; synchronisation; synchronous reference frame phase locked loop; DC offset; small-signal state-space model; SRF-PLL; DC injection; systematic design method; grid interconnection standard; prefilter-based design; transient response; low-end digital controller
A novel small-signal state-space model is formulated for the commonly used synchronous reference frame phase-locked loop (SRF-PLL). Using this model, the effect of dc offsets as a function of SRF-PLL design parameters is quantified. It is shown that the unit vectors produced by the phase-locked loop (PLL) will have dc offsets when the input contains dc offsets. This can result in dc injection to the grid, which is highly undesirable. A systematic design method is proposed which ensures that dc injection to the grid is within the prescribed grid interconnection standards. In this design, SRF-PLL bandwidth is analytically computed for different levels of dc offsets in the input. The proposed design is compared with conventional pre-filter-based designs addressing the dc offset issue. The proposed design method results in the fastest transient response for given worst-case input dc offset without changing the PLL structure. Such a design for the SRF-PLL is computationally less intensive and is preferable when low-end digital controllers are used. The analytical results have been verified experimentally.
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