Hysteresis Reduction in Negative Capacitance Ge PFETs Enabled by Modulating Ferroelectric Properties in HfZrOx

We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrOx (HZO) by changing the post annealing temperature. As annealing temperature varies from 350 degrees C to 450 degrees C, HZO exhibits a significant increasing in the ratio of remnant polarization P-r to coercive field E-c, which results in the improvement of the magnitude of ferroelectric NC C-FE, therefore contributing to the reduction of hysteresis of the ferroelectric NC Ge transistors. It is also reported that the NC Ge transistor annealed at 450 degrees C has a small hysteresis of 0.10 V, and achieves the improved SS and I-DS compared to control device without HZO.