期刊
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
卷 6, 期 1, 页码 996-1006出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JEDS.2018.2821763
关键词
Cryogenic electronics; CMOS; cryogenic; cryo-CMOS; characterization; modeling; kink; 4 K; LNA
资金
- Intel Corp.
Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-mu m and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.
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