Fitting Cells Into a Narrow VT Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

This paper presents an in-depth comparative analysis of the major physical constraints to the width of the threshold-voltage distribution of a state-of-the-art NAND Flash array. The analysis addresses both time-0 placement by program-and-verify algorithms on fresh and cycled arrays and distribution widening during idle/bake periods. Results allow to identify how each physical effect impacts the threshold-voltage distribution as a function of array program conditions, temperature, cycling, and duration of idle/bake periods, providing clear hints for the design of next generation technology nodes.