Pulse swallowing frequency divider with low power and compact structure

A pulse swallowing frequency divider with low power and compact structure is presented. One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal, and automatically powered off when it has no contribution to the operation of the prescaler. The DFFs in the program counter and the swallow counter are shared to compose a compact structure, which reduces the power consumption further. The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 x 22 mu m(2). The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.