4.5 Article

Low-Crosstalk Fabrication-Insensitive Echelle Grating Demultiplexers on Silicon-on-Insulator

期刊

IEEE PHOTONICS TECHNOLOGY LETTERS
卷 27, 期 5, 页码 494-497

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LPT.2014.2377075

关键词

Complementary metal-oxide-semiconductor (CMOS); echelle gratings (EGs); photonic integrated circuits (PICs); silicon-on-insulator (SOI); silicon photonics

资金

  1. French National Program Programme d'Investissements d'Avenir through the l'Institut de Recherche Technologique [ANR-10-AIRT-05]

向作者/读者索取更多资源

In this letter, we report about design, fabrication, and testing of echelle grating (EG) demultiplexers in the O-band (1.31-mu m) for silicon-based photonic integrated circuits. In detail, flat band perfectly chirped EGs and two-point stigmatic EGs on the 300-nm thick silicon-on-insulator platform designed for 4 x 800-GHz spaced wavelength-division multiplexing featuring a low average crosstalk (-30 dB), a precise channel spacing, optimized interchannel uniformity (0.7 dB) and insertion losses (3-3.5 dB) are presented. Wafer-level statistical performance analysis shows the EG spectral response to be stable over the wafer in terms of crosstalk, channel spacing, and bandwidth with minimal wavelength dispersion (<0.8 nm), thus highlighting the intrinsic robustness of high-order gratings and chosen fab pathways as well as the full reliability of 3-D vectorial modeling tools.

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