THE ALADDIN APPROACH TO ACCELERATOR DESIGN AND MODELING

THE AUTHORS DEVELOPED ALADDIN, A PRE-RTL, POWER-PERFORMANCE ACCELERATOR MODELING FRAMEWORK AND DEMONSTRATED ITS APPLICATION TO SYSTEM-ON-CHIP (SOC) SIMULATION. ALADDIN ESTIMATES PERFORMANCE, POWER, AND AREA OF ACCELERATORS WITHIN 0.9, 4.9, AND 6.6 PERCENT WITH RESPECT TO REGISTER-TRANSFER LEVEL (RTL) IMPLEMENTATIONS. INTEGRATED WITH ARCHITECTURE-LEVEL GENERAL-PURPOSE CORE AND MEMORY HIERARCHY SIMULATORS, ALADDIN PROVIDES A FAST BUT ACCURATE WAY TO MODEL ACCELERATORS' POWER AND PERFORMANCE IN AN SOC ENVIRONMENT.