期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 50, 期 1, 页码 68-80出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2014.2348311
关键词
AD-PLL; CMOS; DAC; digital varactor; dual loop; edge injection; gated injection; injection-locking; logic synthesis; low jitter; low power; PLL; PVT; small area; standard cell; synthesizable
资金
- MIC
- SCOPE
- MEXT
- STARC
- STAR
- VDEC
- Cadence Design Systems, Inc.
- Synopsys, Inc.
- Mentor Graphics, Inc.
This paper presents a fully synthesizable phaselocked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 mu m x 60 mu m layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 mu W DC power.
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