4.6 Article

A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications

期刊

IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 50, 期 7, 页码 1669-1679

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2015.2411623

关键词

CMOS integrated circuits; injection-locked oscillators; local oscillators; millimeter-wave integrated circuits; phase-locked loops; phase noise

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This paper presents an original mmW frequency multiplier that provides the channel center frequencies of the IEEE 802.15.3c standard from a much lower and fixed frequency of 2.16 GHz. It is composed of a voltage-controlled oscillator (VCO) whose supply is periodically switched on-and-off by the input signal, providing Periodically Repeated Oscillations Train (PROT). This multi-harmonic signal is injected into an oscillator (ILO) that locks onto the harmonic of interest, providing a continuous wave sinusoidal signal in the 60 GHz band. The CMOS 40 nm circuit consumes 32 mW and occupies only 0.07 mm. A theoretical approach on the synchronization of the PROT signal generator and the ILO is proposed, based on custom approximated solutions of the Van der Pol oscillator and highlighting new synchronization phenomena. Based on this theory, this novel programmable multiplication technique requires a unique fixed low frequency reference to perform multi-channel mmW LO generation. The phase noise of the output LO signal is only limited by the input low frequency reference phase noise and the frequency ratio between the output and the input signals. Thus, a 60 GHz signal has been generated with this technique with a record phase noise of -104 dBc/Hz@ 1 MHz offset.

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