期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 50, 期 11, 页码 2635-2644出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2015.2466443
关键词
All-digital delay-locked loop (ADDLL); cyclic half-delay-line architecture; low power; small area; wide range; 2b-per-stage asynchronous binary search circuit (2b-ABS)
资金
- Ministry of Education
- National Science Council, Taiwan [NSC 102-2221-E-194-061-MY3]
A 3 MHz-to-1.8 GHz, 94 mu W-to-9.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology is presented. In this paper, a cyclic half-delay-line architecture that uses the same type of delay lines for cyclic delay determination and coarse locking is proposed and used to achieve the design goals of small footprint and fast locking for a large operating frequency range. In addition, a new delay structure is developed for the cyclic delay units and coarse delay line. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, the automatic bypassing of the cyclic operation is developed and used to reduce power consumption during high-frequency operation. Through the use of proposed techniques, the active area is reduced to only 0.0153 mm(2), and the operating frequency range is from 3 MHz to 1.8 GHz. The measurement results show that the proposed ADDLL achieves a peak-to-peak jitter of 3 ps with 9.5 mW power consumption when operated at 1.8 GHz.
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