期刊
IEEE ELECTRON DEVICE LETTERS
卷 36, 期 12, 页码 1329-1331出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2015.2489655
关键词
a-IGZO; bulk-accumulation; offset; ring-oscillator; TFT
资金
- Industrial Strategic Technology Development Program - MOTIE/KEIT [10045269]
The overlap between gate and source/drain electrodes gives rise to parasitic capacitance (C-gd), which causes RC signal delay in thin-film transistor (TFT) circuits. Here, we show that in amorphous-indium-gallium-zinc-oxide TFTs, offsets as large as 0.5 mu m, result in only slight reductions in drain-current, such that (compared with single-gate TFTs with 2.5-mu m gate-to-source/drain overlaps) an overall three times increase in switching speed can be achieved in dual-gate TFTs with offset top-gates shorted to offset bottom-gates. The high switching speed (similar to 18 ns/stage delay), which is a combined effect of the bulk-accumulation achieved by shorting the two gates and zero C-gd, results in high-speed amorphous oxide TFT-based circuits.
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