期刊
IEEE ELECTRON DEVICE LETTERS
卷 36, 期 7, 页码 663-665出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2015.2429680
关键词
III-V MOSFETs; InAs; VLS growth; nanowire; selective lateral epitaxy
资金
- National Science Foundation ECCS Award [1001928]
- DMR Award [1006581]
- Directorate For Engineering
- Div Of Electrical, Commun & Cyber Sys [1001928] Funding Source: National Science Foundation
- Division Of Materials Research
- Direct For Mathematical & Physical Scien [1006581] Funding Source: National Science Foundation
High indium content III-V materials are one of the most promising candidates for beyond Si CMOS technologies. We present InAs planar nanowire (NW) MOSFETs grown directly on a semi-insulating GaAs (100) substrate by the selective lateral epitaxy (SLE) method via the metal-seeded planar vapor-liquid-solid mechanism. Despite a similar to 7% lattice mismatch, in-plane and self-aligned single-crystal InAs NWs are grown epitaxially on GaAs. Such heterogeneous SLE provides a potential solution for the integration of different channel materials on one substrate. Gate-all-around MOSFET devices are fabricated by releasing the NW channel from the substrate through a combination of digital etching and selective etching processes. The device with a NW width of 30 nm and gate length of 350 nm shows an I-ON/I-OFF ratio of 10(4) and a peak transconductance of 220 mS/mm at V-ds = 0.5 V.
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