3.8 Proceedings Paper

A Parallel BP Neural Network Based on the FPGA

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TRANS TECH PUBLICATIONS LTD
DOI: 10.4028/www.scientific.net/AMM.239-240.1541

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Neural network; Field programmable gate array(FPGA); Back Propagation algorithm; Parallel architecture; System On Programmable Chip(SOPC)

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This paper, with the analysis of BP neural network learning and execution algorithm on single computer unit, a parallel neural network on many computer units is constructed, a system on programmable chip based on FPGA and uClinux is provided. Because it's flexibility and reliability, this parallel neural network can be widely used where there is a large quantity of data to be processed. In addition to it, the system based on the SOPC has good versatility and easy to transplant because the reconfiguration of the hardware logic and software system.

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