Trapping phenomena and degradation mechanisms in GaN-based power HEMTs

This paper reports an overview of the most relevant trapping and degradation mechanisms that limit the performance and lifetime of GaN-based transistors for application in power electronics. Results obtained on state-of the-art devices are described and discussed throughout the paper, with the aim of providing a clear description of the topic. The first part of the paper deals with the issue of dynamic-R-on : after describing a robust test strategy for the analysis of the pulsed characteristics of the devices, we discuss the voltage- and temperature-dependent pulsed I-V characteristics of 650 V-rated transistors, and the physical origin of dynamic R-on in these devices. The results demonstrate that through proper buffer optimization it is possible to reach negligible trapping at high voltage. The properties of the traps responsible for dynamic-R-on are also discussed in detail in the paper, based on drain-current transient data. A specific discussion is devoted to hot-electron trapping processes, that - under hard switching conditions - may lead to significant modifications in the resistance of the 2DEG. The second part of the paper deals with device degradation: based on a wide set of experimental results, we describe the physical mechanisms responsible for the worsening of the properties of the devices. More specifically, we demonstrate that stress in off-state conditions may result in measurable changes in the pinch-off voltage, mostly consisting in a negative-threshold instability (NBTI). The origin of this shift is discussed in detail; we also demonstrate that in a real-life cascode configuration (where a low, subthreshold leakage current flows through the device in the off-state), NBTI effects are mitigated. Finally, we discuss the stability of the gate-stack, induced by the exposure to positive gate bias.